1. Field of the Invention
The present invention relates to a logic circuit system utilizing programmable logic circuits that can reconfigure their circuit configuration and change their circuit functions during operation.
2. Description of the Related Art
Where a circuit performing processing consisting of plural process steps is made up of one integrated circuit, the processing capability of some portions of the integrated circuit are superfluous. Correspondingly, excess electric power is consumed, because the operating speed of the whole integrated circuit is set to be capable of performing the processing of the process step that requires the highest processing capability in spite of the fact that there are process steps requiring only low processing capability.
An effective technique of reducing the power consumption of an integrated circuit is to lower the operating voltage and the frequency of the clock signal (i.e., clock frequency). However, where the operating voltage is lowered, the upper limit of the operable clock frequency is reduced. Where the clock frequency is lowered, the processing capability is reduced.
In recent years, programmable logic circuits capable of changing their circuit functions during operation have been proposed. Such a programmable logic circuit can change the circuit configuration of the whole or part of the circuit during operation of the circuit. Programmable logic circuits include FPGAs (field programmable gate arrays) capable of changing their logic configurations at high speed and DPGAs (dynamically programmable gate arrays). These arrays are hereinafter referred to simply as “programmable logic circuits”.
Conventionally, a technique in which unit circuits for executing processing steps corresponding to plural process steps, respectively, are configured on a programmable logic circuit in a time-shared manner to process all the process steps has been proposed in Japanese Patent Application (KOKAI) No. 2001-202236.
With the aforementioned technique for operating a programmable logic circuit in a time-shared manner, a surplus of processing capability can be reduced by operating unit circuits corresponding to process steps requiring high processing capability for long periods and by operating unit circuits corresponding to process steps requiring only low processing capability for short periods.
With this technique, however, it is necessary to appropriately set the proportions of the operating times of the unit circuits in advance. That is, it is not assumed that the technique copes with a case where the processing capabilities respectively imposed on the unit circuits vary dynamically.